1. Field of the Invention
The present invention relates to a semiconductor memory and, in particular, to a memory cell structure having improvements in resistance to soft error of a MOS static RAM.
2. Description of the Background Art
As the miniaturization of memory cells proceeds, the following soft error problem becomes noticeable. Specifically, the data stored in a storage node is inverted due to electrons generated from alpha rays released from a package and neutron beams from outer space. Particularly, as power supply voltage is lowered, malfunction becomes more significant. Attempts to reduce soft error are being pursued.
FIG. 37 is a circuit diagram illustrating a structure equivalent to a SRAM memory cell disclosed in, for example, Japanese Patent No. 2589949. As shown in FIG. 37, a memory cell 100 is made up of PMOS transistors PT1 and PT2, and NMOS transistors NT5 to NT8, NT11, NT12, NT21 and NT22.
The sources of the PMOS transistors PT1 and PT2 are both connected to a power supply voltage Vcc. The drain of the PMOS transistor PT1 is connected through a node 101 to the gate of the PMOS transistor PT2 and to the gates of the NMOS transistors NT21 and NT22. The drain of the PMOS transistor PT2 is connected through a node 111 to the gate of the PMOS transistor PT1 and to the gates of the NMOS transistors NT11 and NT12.
The sources of the NMOS transistors NT11 and NT12 are both grounded. The drain of the NMOS transistor NT11 is connected through the node 101 to the drain of the PMOS transistor PT1. The drain of the NMOS transistor NT12 is connected through the nodes 101 and 102 to the drain of the PMOS transistor PT1.
The sources of the NMOS transistors NT21 and NT22 are both grounded. The drain of the NMOS transistor NT21 is connected through the node 111 to the drain of the PMOS transistor PT2. The drain of the NMOS transistor NT22 is connected through the nodes 111 and 112 to the drain of the PMOS transistor PT2.
The NMOS transistor NT5 is interposed between a bit line BL50 and the node 101, and its gate is connected to a word line WL50. The NMOS transistor NT6 is interposed between a bit line BL60 and the node 101, and its gate is connected to a word line WL60. The NMOS transistor NT7 is interposed between a bit line BL51 and the node 111, and its gate is connected to the word line WL50. The NMOS transistor NT8 is interposed between a bit line BL61 and the node 111, and its gate is connected to the word line WL60.
In such a configuration, the word line WL50 or WL60 is brought into the active state and the NMOS transistors NT5 and NT6, or the NMOS transistors NT6 and NT8 are brought into the on state, thereby to provide access to the nodes 101 and 111, each being a storage node. This enables to obtain the data from the paired bit lines BL50 and BL51 or the paired bit lines BL60 and BL61.
In this configuration, a NMOS driver transistor that is usually made up of a single NMOS transistor is divided into two NMOS transistors (which is divided into the NMOS transistors NT11 and NT12, and NT21 and NT22).
In order to divide the storage node serving as the drain of the PMOS transistor PT1 (PT2) into the node 101 (111) and the node 102 (112), the NMOS transistor NT11 (NT21) and the NMOS transistor NT12 (NT22) are oppositely disposed so as to interpose therebetween an N well region where the PMOS transistor PT1 is to be formed.
Therefore, the N well region prevents that a depletion region on the opposite side of the N well region is adversely affected by electrons or holes generated from energy particles colliding with one side of the N well region. This enables to lower incidence of soft error.
However, even with the foregoing SRAM memory cell, a reduction in soft error is insufficient. Further, there is the problem that the circuit configuration is complicated by using two driver transistors, although it can be generally configured by using one.
According to a first aspect of the invention, a semiconductor memory having a memory cell containing first and second inverters subjected to cross connection, a first conductivity type being defined by first kind, and a second conductivity type being defined by second kind, is characterized in that: the first inverter consists of a first field effect transistor of the first kind and a first field effect transistor of the second kind; that the second inverter consists of a second field effect transistor of the first kind and a second field effect transistor of the second kind; and that the first and second field effect transistors of the first kind are disposed in separate first and second well regions of the second kind, respectively.
According to a second aspect of the invention, the semiconductor memory of the first aspect is characterized in that: an output part of the first inverter includes a connecting part between one electrode of the first field effect transistor of the first kind and one electrode of the first field effect transistor of the second kind, an input part thereof includes a connecting part between a control electrode of the first field effect transistor of the first kind and a control electrode of the first field effect transistor of the second kind; an output part of the second inverter includes a connecting part between one electrode of the second field effect transistor of the first kind and one electrode of the second field effect transistor of the second kind, and an input part thereof includes a connecting part between a control electrode of the second field effect transistor of the first kind and a control electrode of the second field effect transistor of the second kind; that the memory cell further includes: (i) a third field effect transistor of the first kind, one electrode of which is connected to a first storage terminal electrically connected to the output part of the first inverter and the input part of the second inverter, and the other electrode of which is connected to a first bit line, and a control electrode of which is connected to a word line; and (ii) a fourth field effect transistor of the first kind, one electrode of which is connected to a second storage terminal electrically connected to the output part of the second inverter and the input part of the first inverter, and the other electrode of which is connected to a second bit line, and a control electrode of which is connected to a word line; and that the third and fourth field effect transistors of the first kind are disposed in second and first well regions of the second kind, respectively.
According to a third aspect of the invention, the semiconductor memory of the second aspect is characterized in that the respective one electrodes in the first to fourth field effect transistors of the first kind are disposed separately.
According to a fourth aspect of the invention, the semiconductor memory of the second aspect is characterized in that: the first and third field effect transistors of the first kind and the first field effect transistor of the second kind are arranged in an approximately straight line along the direction of formation of the word line; and that the second and fourth field effect transistors of the first kind and the second field effect transistor of the second kind are arranged in an approximately straight line along the direction of formation of the word line.
According to a fifth aspect of the invention, the semiconductor memory of the first aspect is characterized in that the first and second field effect transistors of the first kind are arranged so as to be point symmetry with respect to the central point of the memory cell.
According to a sixth aspect of the invention, the semiconductor memory of the second aspect is characterized in that the third and fourth field effect transistors of the first kind are arranged so as to be point symmetry with respect to the central point of the memory cell.
According to a seventh aspect of the invention, the semiconductor memory of the second aspect is characterized in that the width of the control electrode of the first and second field effect transistors of the first kind is set so as to be larger than the width of the control electrode of the third and fourth field effect transistors of the first kind.
According to an eighth aspect of the invention, the semiconductor memory of one of the foregoing aspects is characterized in that the memory cell further includes (i) a first resistance component interposed between the input part of the first inverter and the second storage terminal, and (ii) a second resistance component interposed between the input part of the second inverter and the first storage terminal.
According to a ninth aspect of the invention, the semiconductor memory of the eighth aspect is characterized in that the first and second resistance components include a high resistance metal wiring formed from a metal material having a higher resistivity than CoSi.
According to a tenth aspect of the invention, the semiconductor memory of the eighth aspect is characterized in that the first and second resistance components include a high resistance polysilicon wiring formed from polysilicon having a higher resistivity than CoSi.
According to an eleventh aspect of the invention, the semiconductor memory of the second aspect is characterized in that the control electrodes of the third and fourth field effect transistors of the first kind and the word line are formed by using a single polysilicon.
According to a twelfth aspect of the invention, the semiconductor memory of the second aspect is characterized in that: the word line includes separate first and second word lines; that the control electrode of the third field effect transistor of the first kind is connected to the first word line; and that the control electrode of the fourth field effect transistor of the first kind is connected to the second word line.
According to a thirteenth aspect of the invention, the semiconductor memory of the twelfth aspect is characterized in that: the first bit line includes first and second partial bit lines forming a pair of bit lines; that the second bit line includes third and fourth partial bit lines forming a pair of bit lines; that the third field effect transistor of the first kind includes fifth and sixth field effect transistors of the first kind, the fifth field effect transistor of the first kind being interposed between the first partial bit line and the second storage terminal, the sixth field effect transistor of the first kind being interposed between the second partial bit line and the first storage terminal; and that the fourth field effect transistor of the first kind includes seventh and eighth field effect transistors of the first kind, the seventh field effect transistor of the first kind being interposed between the third partial bit line and the first storage terminal, the eighth field effect transistor of the first kind being interposed between the fourth partial bit line and the second storage terminal.
According to a fourteenth aspect of the invention, the semiconductor memory of the thirteenth aspect is characterized in that the width of the control electrode of the first and second field effect transistors of the first kind is set so as to be larger than the width of the control electrode of the fifth to eighth field effect transistors of the first kind.
According to a fifteenth aspect of the invention, the semiconductor memory of the second, twelfth or thirteenth aspect is characterized in that a region for forming the control electrode of the first and second field effect transistors of the first kind is disposed so as to form a portion of the second and first storage terminals, respectively.
According to a sixteenth aspect of the invention, the semiconductor memory of one of the foregoing aspects is characterized in that: the first and second field effect transistors of the second kind are disposed in a well region of the first kind; and that the well region of the first kind is disposed between the first and second well regions of the second kind.
In the semiconductor memory of the first aspect, the first and second field effect transistors of the first kind are disposed in the separate first and second well region of the second kind, respectively. Therefore, if carriers generated from alpha rays, etc. are collected into one or the other electrode region of one of the first and second field effect transistor of the first kind, such carriers are cancelled by being released from one or the other electrode region of the other of the first and second field effect transistor of the first kind on which no influence of the carriers is exerted. This enables to increase resistance to soft error.
In addition, since the first and second inverters each consists of a combination of a field effect transistor of the first kind and that of the second kind, a complementary type can be realized by at least sufficient circuit configuration.
In the semiconductor memory of the second aspect, the third and fourth field effect transistors of the first kind are disposed in the second and first well regions of the second kind, respectively. Thereby, the memory cell selecting operation by means of the word line, and the write/read operation to the memory cell via the first and second bit lines, are executable while improving resistance to soft error.
In the semiconductor memory of the third aspect, resistance to soft error can be increased by separately forming one electrode to be connected to the first or second storage terminal in the first to fourth field effect transistors of the first kind.
In the semiconductor memory of the fourth aspect, the degree of integration can be increased by virtue of the layout of the first to fourth field effect transistors of the first kind and the first and second field effect transistors of the second kind.
In the semiconductor memory of the fifth aspect, by disposing the first and second MOS transistors so as to be point symmetry with respect to the central portion of the memory cell, arrangement between adjacent memory cells can be facilitated to increase the degree of integration.
In the semiconductor memory of the sixth aspect, by disposing the third and fourth MOS transistors so as to be point symmetry with respect to the central portion of the memory cell, arrangement between adjacent memory cells can be facilitated to increase the degree of integration.
In the semiconductor memory of the seventh aspect, the stability of the memory cell can be increased by setting such that the control electrode width of the first and second field effect transistors of the first kind is larger than that of the third and fourth field effect transistors of the first kind.
In the semiconductor memory of the eighth aspect, by signal propagation delay due to the first and second resistance components, the response characteristic for inverting the data held in the first and second storage terminals of the memory cell can be elongated, thereby soft error is hard to occur.
The semiconductor memory of the ninth aspect realizes the first and second resistance components by using the high resistance polysilicon wiring.
The semiconductor memory of the tenth aspect realizes the first and second resistance components by using the high resistance polysilicon wiring.
In the semiconductor memory of the eleventh aspect, by using a single polysilicon common to the control electrodes and word lines of the third and fourth MOS transistors, the number of layers to be formed can be reduced, thereby allowing for a reduction in the cost of the semiconductor memory.
In the semiconductor memory of the twelfth aspect, by the presence of two memory cell selecting means composed of the first and second word lines, the memory cell can be used for FIFO memory.
The semiconductor memory of the thirteenth aspect realizes a two-port memory cell composed of the first to fourth partial bit lines and the first and second word lines.
In the semiconductor memory of the fourteenth aspect, the stability of the memory cell can be increased by setting such that the control electrode width of the first and second field effect transistors of the first kind is larger than that of the fifth to eighth field effect transistors of the first kind.
In the semiconductor memory of the fifteenth aspect, with the arrangement such that the region for forming the control electrode of the first and second field effect transistors of the first kind forms a portion of the second and first storage terminals, respectively, the region for forming memory cell can be narrowed to increase the degree of integration.
In the semiconductor memory of the sixteenth aspect, by the well region of the first kind disposed between the first and second well regions of the second kind, it is avoided that carriers generated in the first or second well region of the second kind exert influence on the other well region of the second kind.
It is an object of the present invention to overcome the foregoing problem by providing a semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration.